As semiconductor processing technology is highly developed, and a circuit gradually becomes more complicated, the possibility that an error occurs in a design process of a semiconductor also increases. When an error is found after the manufacture of a silicon chip, a mask has to be manufactured again. Thus, in an ultra-integrated process, a cost for error revision is increased, and much time for the error revision is required.
In general, a standard cell includes a plurality of lower metal layers. When an error occurs during the manufacture of a silicon chip, metal layer revision has to be carried out, and the process has to be carried out again from a lower metal layer. Thus, a fabrication time for obtaining a chip is delayed, and the number of masks required to be revised is increased. The delay of a fabrication time and the increase in the number of masks to be manufactured immediately result in an increase in the cost.
In general, when designing and manufacturing a semiconductor chip, a computer aided design (CAD) tool, (i.e., an electronic design automation (hereinafter, referred to as EDA) tool) is used. The EDA tool used in the design of a semiconductor chip can perform a layout process, or an equivalent, as well as a place & route (P&R) process. In the P&R process, a netlist indicating connection information between a cell or a block and a metal layer is configured.
A method for interconnection between a block to be repaired due to an error and a spare block includes a standard metal method and a programmable interconnection method.
The standard metal method is a technique of previously disposing a mesh-structured wire matrix, and revising and connecting a vertical interconnect access (via) on the wire matrix when a repair is required.
In the standard metal method, it is possible to revise a metal layer by correction of a via. However, the mesh-structured wire matrix has to be formed in proportion to the number of interconnections between blocks or cells, thereby drastically increasing routing overhead.
The programmable interconnection method is a technique of connecting a spare block and a block to be repaired by a switch block, in which the spare block is connected instead of the block that has an error so as to revise the error.
In the programmable interconnection method, a plurality of switch blocks are required, and also when the number of interconnections is changed, a programmable interconnection block is required to be generally changed. Also, in the programmable interconnection method, an area occupied by a programmable interconnection block for the revision of a metal layer is larger than a block for an original function. Accordingly, this method is inefficient because the power consumption and delay are highly increased due to the use of the programmable interconnection block.